- Chip architecture and logic design.
- Analyzes chip failures, and debugs chip problems.
-Plan the Chip Architecture & placement.
- Memory cell, Single cell, Block & full chip circuit design, simulation and optimization.
- RC extraction from layout, and perform post-layout simulation, circuit optimization.
-Manage the layout planning.
-Work with layout designer to optimize layout
-Analyzes chip failures, and debugs chip problems.
- Principles and techniques of electrical engineering
-Knowledge of defining DRAM /SRAM architecture, and high speed/Low power DRAM /SRAM circuit techniques.
-Prefer the DDR experience and high-speed technique design experience.
- Skill for memory simulator such as HSPICE, HSIM, Verilog and layout tool & verification software.
- Ability of debugging using MOSAID/ADVANTEST tester.
Required education and experience
- Prefer BS in EE
- No design experience, but have excellent educational backgrounds
- Promote teamwork and cooperative effort.
- Maintain a clean, safe, and unobstructed work area, practice good safety habits, and utilize appropriate safety equipment.
- Understand and apply appropriate quality improvement processes.
- Candidate must have good organization skills and an ability to work productively both independently and in a team environment.
- Strong verbal and written communication skills.
- Strong problem solving skills.
- Ability to exercise independent judgment.
- Competence in time management.
- Demonstrated ability to interface and coordinate work with all levels and other departments