Memory Design Engineer (Career Level/ Entry Level)

芯成半导体(上海)有限公司
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信息来源:浙江工业大学毕业生就业信息网 温馨提示:求职需提高谨慎,辨别信息真伪,勿上当受骗。
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Job description:
- Chip architecture and logic design.
- Analyzes chip failures, and debugs chip problems.
-Plan the Chip Architecture & placement.
- Memory cell, Single cell, Block & full chip circuit design, simulation and optimization.
- RC extraction from layout, and perform post-layout simulation, circuit optimization.
-Manage the layout planning.
-Work with layout designer to optimize layout
-Analyzes chip failures, and debugs chip problems.
Required knowledge,skills,abilities
- Principles and techniques of electrical engineering
-Knowledge of defining DRAM /SRAM architecture, and high speed/Low power DRAM /SRAM circuit techniques.
-Prefer the DDR experience and high-speed technique design experience.
- Skill for memory simulator such as HSPICE, HSIM, Verilog and layout tool & verification software.
- Ability of debugging using MOSAID/ADVANTEST tester.

Required education and experience
- Prefer BS in EE
- No design experience, but have excellent educational backgrounds
-Additional requirements(knowledge,skills,abilities,certifications,language)
- Promote teamwork and cooperative effort.
- Maintain a clean, safe, and unobstructed work area, practice good safety habits, and utilize appropriate safety equipment.
- Understand and apply appropriate quality improvement processes.
- Candidate must have good organization skills and an ability to work productively both independently and in a team environment.
- Strong verbal and written communication skills.
- Strong problem solving skills.
- Ability to exercise independent judgment.
- Competence in time management.
- Demonstrated ability to interface and coordinate work with all levels and other departments

芯成半导体(上海)有限公司是由总部设在美国加州硅谷的ISSI公司在中国大陆设立的一家全资跨国公司。于二000年九月在上海正式注册成立,注册资本为1791.25万美元。主要从事高性能集成电路存储器及其相关器件的设计、制造和销售。目前在苏州、北京、深圳也均设有分支机构。
我们不仅拥有先进的硬件设施、超前的管理体系和和谐的工作氛围,而且还拥有独具竞争力的薪资和福利报酬。欢迎同学们踊跃投递!